1. Technical Field
The present invention relates in general to data processing and, in particular, to data processing in a processor. Still more particularly, the present invention relates to the use of instruction destination tags within a processor.
2. Description of the Related Art
In conventional superscalar processors, instructions are executed in parallel in multiple execution units, possibly out-of-order with respect to the predefined program order. As the instructions are executed, results of execution are generated and buffered at various locations within the processor for later reference. Because subsequent instructions are often dependent upon the results of previous instructions, a dependency tracking scheme is generally employed to ensure that all data dependencies between instructions are observed.
In one prior art implementation, dependencies between instructions are managed through the use of multiple different destination tags. In such prior art implementations, a different destination tag is defined for each location within the processor that will be updated as a result of instruction execution. Comparison of destination tags of the various instructions thus permits the processor to detect and observe dependencies between instructions. However, the total number of destination tags that must be tracked and routed within the prior art processor is potentially equal to the product of the number of instructions in flight multiplied by the number of destinations of the instruction results. Tracking and routing such a large number of destination tags within the processor entails considerable circuitry within the processor and consumes significant power.
In view of the shortcomings of prior art techniques of dependency tracking within conventional processors, the present invention recognizes that it would be useful and desirable to provide an improved processor and method of dependency tracking within a processor utilizing instruction destination tags.